Detecting faults in CMOS (Complimentary Metal Oxide Silicon) ICs (Integrated Circuits) is critical to assure correct functioning of the IC during use. Common types of faults that must be detected are stuck-open or stuck-closed nodes which can adversely affect the circuit operation. FIG. 1 illustrates a typical CMOS invertor circuit formed in the active face of a semiconductor wafer. PMOS transistor 2 and NMOS transistor 4 are connected in series between power supply Vcc, typically at 5V, and power supply Vss, typically grounded at 0V. The gates of the two transistors are connected together at node A. The output is taken from the series connection at node B. Invertors 6 and 8 are merely repetitions of the invertor circuit defined by transistors 2 and 4 shown in logical symbol format for clarity. Invertor 6 can represent the output stage of a register or latch which can be directly controlled by signals external to the integrated circuits. Invertor 8 can represent the input stage of a register or latch which has an externally observable output.
Under normal, non-fault conditions when the output of previous invertor stage 6 is high, i.e. at approximately Vcc, very little current, I.sub.IN flows. Node A remains at the same high potential, keeping PMOS transistor 2 in an off state; hence I.sub.D is very low, and restricted to the leakage current of the PMOS transistor. Similarly, when the output of invertor 6 is low, i.e. at approximately V.sub.SS or OV, I.sub.IN is very small. Node A is held low, keeping NMOS transistor 4 in an off state; hence, I.sub.D is very low and restricted to the leakage current of the NMOS transistor. Hence, in such a circuit, regardless of the logic state, the quiescent current should be very low. For a typical integrated circuit with ten thousand invertors, the total quiescent current, I.sub.CCQ, should be in the range of microAmps, for a no-fault situation.
Under normal non-fault quiescent conditions, the sum of the I.sub.D and I.sub.IN current is typically in the range of a few tenths of nanoAmps. The sum of all the I.sub.D currents for all the circuits in a given integrated circuit is known as the ICC current; and in the quiescent or steady state is known as the I.sub.CCQ current.
FIG. 2 illustrates the same circuit as FIG. 1 having a common fault condition which can be detected by traditional I.sub.CCQ testing. The fault is caused by undesirable resistive element 10 causing a partial short between node A of the circuit and the Vss supply line. Resistive element 10 could be caused by imperfections in the silicon structure, or by contamination of the structure during processing for example. The partial short caused by resistive element 10 creates a current path between node A and Vss, thus causing excessive I.sub.IN current flow. The partial short also tends to pull node A low, thus allowing PMOS transistor 2 to turn on. This results in a large I.sub.D current flow. Rather than a quiescent current range in the nanoAmps, the fault illustrated in FIG. 2 results in a quiescent current in the range of hundreds of microAmps or milliAmps. This type of fault can easily be detected by conventional I.sub.CCQ testing methods. A partial short between a node and the Vcc power supply results in the same level of anomalous quiescent current and is hence also readily detectable. Therefore in the case of a fault condition caused by a short or partial short between a node and a power supply, I.sub.CCQ testing methods can detect the fault by detecting excessive current flow.
With the rapidly increasing density of circuitry on modern ICs, many of which are inaccessible to the external pins, improved techniques are required to test and detect stuck node faults. Conventional I.sub.CCQ testing fails to detect nodes which have lost their connection to Vcc or Vss. A method of discharging these nodes is needed in order to detect this class of faults.